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EM250
“acknowledged” in the same way as the INT_FLAG register—by writing a 1 into the corresponding bit to be
cleared.
If another enabled interrupt occurs after being acknowledged but while interrupts remain disabled, the CPU
will be re-interrupted to service it when the software ISR returns and interrupts are re-enabled.
Applications only have write access to certain bits in the top-level INT_FLAG , INT_CFG , and INT_MISS
registers that pertain to application peripherals. They have full access to second-level INT_periphFLAG and
INT_periphCFG registers for application peripherals. System peripheral events and masking are protected
from application interference.
Applications can also trigger a software interrupt by writing into the INT_SWCTRL register. System software is
responsible for processing and acknowledging this interrupt.
The EM250 also provides a global INT_EN enable bit to enable or disable all interrupts into the CPU. This bit
can be used to easily protect brief critical sections in application or system software.
INT_EN [0x4618]
5.6.1
Registers
15
0-R
0
0
0-R
7
14
0-R
0
0
0-R
6
13
0-R
0
0
0-R
5
12
0-R
0
0
0-R
4
11
0-R
0
0
0-R
3
10
0-R
0
0
0-R
2
9
0-R
0
0
0-R
1
8
0-R
0
INT_EN
0-RW
0
INT_EN
120-0082-000V Rev 1.1
[0]
IRQ enable to CPU.
Page 102
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